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J-Link WiFi
J-Link WiFi is a USB powered JTAG debug probe supporting a large number of CPU cores. Based on a 32-bit RISC CPU, it can communicate at high speed with the supported target CPUs. J-Link is used around the world in tens of thousand places for development and production (flash programming) purposes.
The J-Link debug probes are supported by all major IDEs including Eclipse, GDB-based IDEs and SEGGER Embedded Studio. For a complete list, please refer to Supported IDEs. Including all models, more than 500,000 J-Links have been shipped so far, making J-Link probably the most popular debug probe for ARM cores and the de-facto standard.
Why Use J-Link WiFi?
J-Flash
J-Flash is a PC software to program internal and external flash memory of a microcontroller-based embedded system via J-Link or Flasher. J-Flash is running on Windows systems.
Ozone – J-Link Debugger
Ozone is the debugger for J-Link and J-Trace. It includes all well-known debug controls and information windows and makes use of the best performance of J-Link and J-Trace debug probes.
Flash Breakpoints
The J-Link software comes with an additional feature, called Unlimited Flash Breakpoints. Unlimited Flash Breakpoints allow the user to set an unlimited number of breakpoints when debugging in flash memory.
Further Advantages
- Built-in VCOM functionality
- Comes with integrated licenses for: Unlimited breakpoints in flash memory (Unlimited Flash Breakpoints), RDI / RDDI and J-Flash
- Supports a broad range of microcontrollers
- Multiple CPUs supported—8051, PIC32, RX, ARM7/9/11, Cortex-M/R/A, RISC-V
- Supports direct download into RAM and flash memory
J-Link WiFi Licensing
J-Link WiFi comes with licenses for all J-Link related SEGGER software products: J-Link Unlimited Flash Breakpoints, J-Link RDI / RDDI, J-Flash, J-Link GDB Server, providing the optimum debugging solution for professional developers.
J-Link WiFi can be used with almost all ARM debuggers, enabling download to flash memory with an unlimited number of breakpoints when debugging programs located in flash memory of most popular ARM microcontrollers. It also comes with the license to use J-Flash, SEGGER's popular flash programming software.
SEGGER J-Link Flash Breakpoint Introduction
SEGGER J-Flash Introduction
| Specification | Value | ||||
|---|---|---|---|---|---|
| Supported OS | Microsoft Windows 2000, XP, 2003, Vista, 7 and newer Linux macOS 10.5 and higher | ||||
| Electromagnetic compatibility (EMC) | EN 301 489-1/-17, EN 300 328, EN 62368 | ||||
| Operating temperature | +5°C ... +60°C | ||||
| Storage temperature | -20°C ... +65 °C | ||||
| Relative humidity (non-condensing) | Max. 90% rH | ||||
| Mechanical | |||||
| Size (without cables) | 103mm x 53mm x 28mm | ||||
| Weight (without cables) | 70g | ||||
| Available Interfaces | |||||
| WiFi interface | IEEE 802.11 a/b/g/n (2.4 GHz) | ||||
| USB interface | USB 2.0 (Hi-Speed) | ||||
| Target interface | JTAG / SWD 20-pin | ||||
| JTAG/SWD Interface, Electrical | |||||
| Power supply | USB powered, max. 220mA@5V | ||||
| Target interface voltage (VIF) | 1.2V ... 5V | ||||
| Current drawn from target voltage sense pin (VTRef) | < 25µA | ||||
| Target supply voltage | 5V (derived from USB voltage) | ||||
| Target supply current | Max. 300mA | ||||
| Reset type | Open drain. Can be pulled low or tristated | ||||
| Reset low level output voltage (VOL) | VOL <= 10% of VIF | ||||
| For the whole target voltage range (1.2V <= VIF <= 5V) | |||||
| LOW level input voltage (VIL) | VIL <= 40% of VIF | ||||
| HIGH level input voltage (VIH) | VIH >= 60% of VIF | ||||
| For 1.2V >= VIF <= 3.6V | |||||
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF | ||||
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF | ||||
| For 3.6 <= VIF <= 5V | |||||
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF | ||||
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF | ||||
| JTAG/SWD Interface, Timing | |||||
| Target interface speed | Max. 15 MHz | ||||
| SWO sampling frequency | Max. 30 MHz | ||||
| Data input rise time (Trdi) | Tfdi <= 20ns | ||||
| Data output rise time (Trdo) | Trdo <= 10ns | ||||
| Data output fall time (Tfdo) | Tfdo <= 10ns | ||||
| Clock rise time (Trc) | Trc <= 3ns | ||||
| Clock fall time (Tfc) | Trc <= 3ns | ||||
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